Research · Aman Pathak

/exp experience

PhD Scholar · 2026–present

BITS Pilani KK Birla Goa Campus - CSIS Dept, Hardware Security & Computer Architecture

Hardware security of RISC-V architectures, side-channel attack mitigation, and formal verification of cache coherency protocols
Investigating CXL memory fabric security, coherence directory attacks, and fabric-amplified Row Hammer
Security-aware architectural certification testing (SecACT) for RISC-V and microarchitectural side-channel analysis

Undergraduate Researcher · May–Aug 2025

BITS Pilani / ENineHQ Technologies - Hardware Security & Malware Analysis

Hardware security of RISC-V architectures, side-channel attack mitigation (masking, hiding, dual-rail logic), cryptographic implementations
Formal automata-based modeling of software-managed cache coherency using RISC-V Zicbom extension - proved coherency verification decidable for bounded programs with 58.8% average CMO reduction on embedded benchmarks
Malware analysis using high-dimensional ML on embedded system binaries

Undergraduate Researcher · Feb 2023–Aug 2024

KIIT University - RF & Antenna Systems

Designed Ku/X-band microstrip patch antennas in CST Studio for THz/GHz RF communication
Built Python-based GUI for ASCII data preprocessing; deep learning for antenna parameter optimisation

/ip patents

DFI Monitor (202631036811)

Hardware Data-Flow Integrity Monitor with Register-File Provenance Tagging for RISC-V IoT Processors

Fusion Engine (202631036816)

Programmable Instruction Fusion Engine with SRAM-Based Rules Table for RISC-V IoT Processors

HPC Malware (202631036812)

Hardware-Accelerated Microarchitectural Event Classifier with Programmable Feature Extraction Pipeline and On-Chip Ensemble Inference Engine for Real-Time Malware Detection in RISC-V Processors

Crypto Engine (202631036813)

Per-Peripheral Cryptographic Session Engine with Hardware Key Rotation for RISC-V IoT System-on-Chip

NUMA (202631036815)

RISC-V Processor Architecture with Tiered-Memory ISA Extension, Tier-Aware TLB, and Thunderbolt-Attached External DRAM Expansion with RISC-V Bridge Controller for Linux-Based Heterogeneous Memory Systems

Trace BDT (202631036814)

On-Chip Binary Decision Tree Inference Engine Integrated with RISC-V Trace Encoder for Real-Time IoT Security Monitoring

/papers publications

Memory Security: From Cold Boot Attacks to Side-Channel Defenses

J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · 11th ICTIS, Springer LNNS, 2026

Systematic review of memory encryption for volatile RAM protection. Covers Intel TME/MK-TME, AMD SME, Merkle tree integrity, and side-channel countermeasures against DPA/SPA, bus sniffing, cold boot attacks, and address-pattern analysis in multi-tenant environments.

Formal Verification of Software-Managed Cache Coherency for RISC-V Heterogeneous Embedded Systems

J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · SmartCom, Springer LNNS, 2026

Formal automata-based model for software-managed cache coherency using the RISC-V Zicbom extension. Characterizes necessary and sufficient conditions for safe DMA operations. Proves coherency verification decidable for bounded programs. Achieves 58.8% average CMO reduction on embedded benchmarks including sensor fusion and edge NN inference.

RV-JOSH: A Hardened Operating System for RISC-V based on Java

J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · SmartCom, Springer LNNS, 2026

RISC-V OS with kernel written entirely in Java via JNI. User processes are Java programs loaded as OS processes. Dual-layer malware detection: static bytecode analysis (n-gram opcode features + random forest/NN classifiers) and runtime monitoring via QEMU-augmented HPCs. Page-level memory encryption with selective encryption and periodic rekeying for SPA/DPA resistance on IoT deployments.

Cache and Speculative Side Channel Attacks: A Comprehensive Review

J. Mishra, S.K. Sahay, A. Pathak · ICT4SD, Springer LNNS, Vol.2 pp.219–233, 2025

Trace of microarchitectural side-channel attack evolution: Prime+Probe → Flush+Reload → Spectre V1/V2 → Meltdown → Foreshadow → ZombieLoad → RIDL → CacheOut → BranchScope → Apple Silicon attacks. Analyzes mechanisms, exploitation environments, and security implications. Systematic evaluation of hardware, compiler, and OS mitigation strategies with analysis of the security-performance trade-off.

A Hardware Security Review of RISC-V

J. Mishra, S.K. Sahay, A. Pathak · ICT4SD, Springer LNNS, Vol.2 pp.409–422, 2025

Examination of security vulnerabilities across the open RISC-V ecosystem: microarchitectural side channels, trusted execution environments, secure boot, cryptographic ISA extensions (Zk), memory encryption, and EM fault injection. Contextualizes risks for RISC-V adoption in security-critical applications and national processor initiatives.