Aman Pathak
वज्रदेवम् · vajradevam
PhD scholar in hardware security and computer architecture at BITS Pilani, KK Birla Goa Campus. I break and defend RISC-V microarchitecture: side channels, memory encryption, formal verification. More about me.
Research
- ARCHER: A Cycle-Accurate RISC-V Emulator for Microarchitectural Side-Channel and Memory-Encryption Research
Computers (MDPI), Vol. 15, Issue 8, p. 479, 2026
- PACE: A Page-Adaptive, Cache-Anchored Memory-Encryption Engine for RISC-V with Formally-Verified nth-Order DPA Resistance
Chips (MDPI), Vol. 5, Issue 3, p. 25, 2026
- Novel Microarchitectural Side-Channel Attacks on Open-Source RISC-V Cores
Chips (MDPI), Vol. 5, Issue 3, p. 29, 2026
Selected projects
- whale Minimal container runtime using Linux namespaces, cgroups v2, seccomp-BPF, and overlayfs from scratch
- vajrip Userspace TCP/IP stack: Ethernet, ARP, IP, ICMP, UDP, TCP from scratch, Linux TAP
- memoria malloc/free replacement, segregated free list, mmap heap, leak detection, 57 tests
- nook Tiny embedded ordered key/value database with SQL and auth, built from scratch
- mridu Bytecode VM interpreter in Go
- commodore64 Cycle-accurate 6502 CPU, VIC-II text-mode graphics, PRG loading