Research

Experience
PhD Scholar · 2026-present
BITS Pilani KK Birla Goa Campus - CSIS Dept, Hardware Security & Computer Architecture
  • Hardware security of RISC-V architectures, side-channel attack mitigation, and formal verification of cache coherency protocols
  • Investigating CXL memory fabric security, coherence directory attacks, and fabric-amplified Row Hammer
  • Security-aware architectural certification testing (SecACT) for RISC-V and microarchitectural side-channel analysis
Undergraduate Researcher · May-Aug 2025
BITS Pilani / ENineHQ Technologies - Hardware Security & Malware Analysis
  • Hardware security of RISC-V architectures, side-channel attack mitigation (masking, hiding, dual-rail logic), cryptographic implementations
  • Formal automata-based modeling of software-managed cache coherency using RISC-V Zicbom extension - proved coherency verification decidable for bounded programs with 58.8% average CMO reduction on embedded benchmarks
  • Malware analysis using high-dimensional ML on embedded system binaries
Undergraduate Researcher · Feb 2023-Aug 2024
KIIT University - RF & Antenna Systems
  • Designed Ku/X-band microstrip patch antennas in CST Studio for THz/GHz RF communication
  • Built Python-based GUI for ASCII data preprocessing; deep learning for antenna parameter optimisation
Patents
DFI Monitor (202631036811)
Hardware Data-Flow Integrity Monitor with Register-File Provenance Tagging for RISC-V IoT Processors
Fusion Engine (202631036816)
Programmable Instruction Fusion Engine with SRAM-Based Rules Table for RISC-V IoT Processors
HPC Malware (202631036812)
Hardware-Accelerated Microarchitectural Event Classifier with Programmable Feature Extraction Pipeline and On-Chip Ensemble Inference Engine for Real-Time Malware Detection in RISC-V Processors
Crypto Engine (202631036813)
Per-Peripheral Cryptographic Session Engine with Hardware Key Rotation for RISC-V IoT System-on-Chip
NUMA (202631036815)
RISC-V Processor Architecture with Tiered-Memory ISA Extension, Tier-Aware TLB, and Thunderbolt-Attached External DRAM Expansion with RISC-V Bridge Controller for Linux-Based Heterogeneous Memory Systems
Trace BDT (202631036814)
On-Chip Binary Decision Tree Inference Engine Integrated with RISC-V Trace Encoder for Real-Time IoT Security Monitoring
Publications
ARCHER: A Cycle-Accurate RISC-V Emulator for Microarchitectural Side-Channel and Memory-Encryption Research
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Computers (MDPI), Vol. 15, Issue 8, p. 479, 2026 SCI-Q1
PACE: A Page-Adaptive, Cache-Anchored Memory-Encryption Engine for RISC-V with Formally-Verified nth-Order DPA Resistance
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Chips (MDPI), Vol. 5, Issue 3, p. 26, 2026 SCI-Q2
Novel Microarchitectural Side-Channel Attacks on Open-Source RISC-V Cores
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Chips (MDPI) under review; revised after first round
A Hardware Security Review of RISC-V
J. Mishra, S.K. Sahay, A. Pathak · Lecture Notes in Networks and Systems (ICT4SD), Vol. 2, pp. 409–422, Springer, 2025 Scopus
Cache and Speculative Side-Channel Attacks: A Comprehensive Review
J. Mishra, S.K. Sahay, A. Pathak · Lecture Notes in Networks and Systems (ICT4SD), Vol. 2, pp. 219–233, Springer, 2025 Scopus
Memory Security: From Cold Boot Attacks to Side-Channel Defenses
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Lecture Notes in Networks and Systems (11th ICTIS), Springer, 2026 accepted · Scopus
Formal Verification of Software-Managed Cache Coherency for RISC-V Heterogeneous Embedded Systems
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Lecture Notes in Networks and Systems, Vol. 1997, pp. 430–442, Springer, 2026 Scopus
RV-JOSH: A Hardened Operating System for RISC-V based on Java
J. Mishra, S.K. Sahay, S. Mishra, A. Pathak · Lecture Notes in Networks and Systems (SmartCom), Springer, 2026 accepted · Scopus
Catching the Set Builder: Hardware Detection of Eviction-Set Construction at the Shared LLC on RISC-V
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · Communications in Computer and Information Science (COCOLE), Springer, 2026 accepted · Scopus
The Replacement Policy Is a Side Channel: Closing the Reload+Refresh Leak at the Policy Level on RISC-V
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · Communications in Computer and Information Science (COCOLE), Springer, 2026 accepted · Scopus
The Walk Is the Channel: Page-Table-Walker Cache Partitioning for Deterministic Domain Isolation on Out-of-Order RISC-V
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · ISED 2026 under review
History Is the Channel: Why Index Coloring Cannot Isolate a History-Based Branch Predictor, and a Warm Per-Domain Fix on Open RISC-V RTL
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · ISED 2026 under review
Closing a Spectre-v1 Cache Leak on BOOM with a Per-Domain Guard
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · ISED 2026 under review
No-Op or No Security? A Backward-Compatible, Discoverable, Fail-Closed Contract for Security Directives in the RISC-V HINT Encoding Space
J. Mishra, S.K. Sahay, S. Mishra, L.K. Vashishtha, A. Pathak · ISED 2026 under review