~/vajradevam/about · :set who?
About
I'm a PhD scholar in the Department of Computer Science and Information Systems at BITS Pilani, KK Birla Goa Campus, working at the intersection of hardware security, RISC-V architectures, and low-level software. My current work spans side-channel mitigation, formal verification of cache coherency, and ML-based malware analysis on embedded binaries. Earlier, I designed Ku/X-band antennas at KIIT, and I have six patents filed in the RISC-V space covering data-flow integrity, crypto engines, and on-chip ML.
Outside of research I spend a lot of time building things close to the metal: a TCP/IP stack from scratch, a malloc replacement, a cycle-accurate 6502 emulator, a container runtime using raw namespaces and seccomp, a bytecode VM in Go, and neural networks built purely from matrix operations. Not an exhaustive list — I keep adding repos as a hobby. I also write about architecture, compilers, and C. And I teach sometimes.
Low-level stuff intrigues me. A C program is nothing but bytes in memory; there is no abstraction beyond that. Sure, memory is made of transistors, and VLSI gives us gates and voltages and whatnot, but C — and the assembly it compiles to — is quite magical. I know exactly what it is going to do, and nothing is hidden. It is the naked, and quite often the bitter, truth. More than low levels per se, to borrow from category theory, I am interested in the stripped-down, non-abstracted, naked-truth stuff.
experience
BITS Pilani KK Birla Goa Campus - CSIS Dept, Hardware Security & Computer Architecture
- Hardware security of RISC-V architectures, side-channel attack mitigation, and formal verification of cache coherency protocols
- Investigating CXL memory fabric security, coherence directory attacks, and fabric-amplified Row Hammer
- Security-aware architectural certification testing (SecACT) for RISC-V and microarchitectural side-channel analysis
BITS Pilani / ENineHQ Technologies - Hardware Security & Malware Analysis
- Hardware security of RISC-V architectures, side-channel attack mitigation (masking, hiding, dual-rail logic), cryptographic implementations
- Formal automata-based modeling of software-managed cache coherency using RISC-V Zicbom extension - proved coherency verification decidable for bounded programs with 58.8% average CMO reduction on embedded benchmarks
- Malware analysis using high-dimensional ML on embedded system binaries
KIIT University - RF & Antenna Systems
- Designed Ku/X-band microstrip patch antennas in CST Studio for THz/GHz RF communication
- Built Python-based GUI for ASCII data preprocessing; deep learning for antenna parameter optimisation
skills
languagesCRustJavaPythonVerilogSystemVerilogVHDLHLSRISC-V/6502 Asmx86 AsmChiselGoPerlHaskellJavaScript
systemsGNU/LinuxOpenBSDGDBValgrindGitDockerVimLaTeXWiresharkCST StudioYosysVerilatorOpenSTA
domainsComputer ArchitectureOSHardware SecuritySide-Channel AnalysisEmbedded SystemsCompilersFormal VerificationVLSI
contact
:!mail vajradevam@gmail.com
:!git clone github.com/vajradevam